module ctrl_unit(
input [5:0] op, func, //insn[31:26], insn[5:0]
output regdst,
alusrc,
memtoreg,
regwrite,
memread,
memwrite,
branch, 
jump, //control signals
output [2:0] op_alu //operation for alu
);

wire rf, lw, sw, beq;

//catagorizing//
and(rf, ~op[5], ~op[4], ~op[3], ~op[2], ~op[1], ~op[0]);
and(lw, op[5], ~op[4], ~op[3], ~op[2], op[1], op[0]);
and(sw, op[5], ~op[4], op[3], ~op[2], op[1], op[0]);
and(beq, ~op[5], ~op[4], ~op[3], op[2], ~op[1], ~op[0]);
and(jump, ~op[5], ~op[4], ~op[3], ~op[2], op[1], ~op[0]);

wire [1:0] aluop; //ALUOp

//giving control signals//
assign regdst = rf;
or(alusrc, lw, sw);
assign memtoreg = lw;
or(regwrite, rf, lw);
assign memread = lw;
assign memwrite = sw;
assign branch = beq;
assign aluop[1] = rf;
assign aluop[0] = beq;


//ALU control block
wire [1:0] mid;
or(mid[0], func[0], func[3]);
and(op_alu[0], mid[0], aluop[1]);

or(op_alu[1], ~func[2], ~aluop[1]);

and(mid[1], aluop[1], func[1]);
or(op_alu[2], aluop[0], mid[1]);

endmodule